volatile char RXbuf[4];

volatile char TXbuf[4];

char TPbuf[4];

bool flag=0;

EX_INTERRUPT_HANDLER(UART_ISR);

void Enable_DMA_UART(void)

{

*pDMA7_CONFIG |= DMAEN;

ssync;

*pDMA8_CONFIG |= DMAEN;

ssync;

}

void Disable_DMA_UART(void)

{

*pDMA7_CONFIG &= ~DMAEN;

ssync;

*pDMA8_CONFIG &= ~DMAEN;

ssync;

}

void Init_DMA_UART(void)

{

Disable_DMA_UART();

*pDMA7_PERIPHERAL_MAP = 0x7000; //p5-66

ssync;

*pDMA7_CONFIG = WNR | WDSIZE_8 | DI_EN | FLOW_AUTO | SYNC;

ssync;

*pDMA7_START_ADDR = (void *)RXbuf;

ssync;

*pDMA7_X_COUNT = 2;

ssync;

*pDMA7_X_MODIFY = 1;

ssync;

*pDMA8_PERIPHERAL_MAP = 0x8000;

ssync;

*pDMA8_CONFIG = WDSIZE_8 | FLOW_AUTO | DI_EN | SYNC;

ssync;

*pDMA8_START_ADDR = (void *)TXbuf;

ssync;

*pDMA8_X_COUNT = 2;

ssync;

*pDMA8_X_MODIFY = 1;

ssync;

}

void Init_UART(int baudrate)

{

int SYSCLK;

int DIV;

Init_DMA_UART();

Enable_DMA_UART();

// start init UART0

*pUART0_GCTL=0x0001;  //p11-31

SYSCLK = (int)Get_Sys_Clk();

DIV = (int)(SYSCLK/16/baudrate);

*pUART0_LCR=DLAB;//p11-21 //DLAB=1 ÔêDí·ÃÎêDLL oíDLH

ssync;

*pUART0_DLL=DIV;

ssync;

*pUART0_DLH=DIV>>8;

ssync;

*pUART0_LCR=WLS(8) ;

ssync;

*pUART0_IER= ERBFI | ETBEI; //  ERBFI: Enable Receiver Buffer Full Interrupt; ETBFI: Enable Transmit Buffer Empty Interrupt //p11-26

ssync;

// map interrupt

*pSIC_IAR1 &= ~0xf0000000; // p4-18, Table 4-3. Peripheral Interrupt Events

*pSIC_IAR1 |=  P15_IVG(10);     // UART ÖD¶Ï¶¨òå

ssync;

// map interrupt

*pSIC_IAR2 &= ~0xf; // p4-18, Table 4-3. Peripheral Interrupt Events

*pSIC_IAR2 |=  P16_IVG(10);     // UART ÖD¶Ï¶¨òå

ssync;

register_handler(ik_ivg10, UART_ISR); // UART ISR -> IVG 10

ssync;

*pSIC_IMASK |= IRQ_DMA7 | IRQ_DMA8;

ssync;

}

/****************************************************************************

* Ãû3Æ ￡ouart_device_write

* 1|Äü ￡o UART·￠Ëíoˉêy

* èë¿ú2Îêy ￡o*buf,len

* ·μ»ØÖμ ￡oÎT

****************************************************************************/

int uart_device_write(char *buf, int len)

{

int i=1;

//delay_Uart(50);

for(i=0;i<len;i++)

{

*pUART0_THR = buf[i];

while(!(*pUART0_LSR&0x20));

}

return i;

}

EX_INTERRUPT_HANDLER(UART_ISR)

{

int i=0;

char temp;

int temp1;

if (IRQ_DMA7 == (IRQ_DMA7 & *pSIC_ISR))

{

//Interrupt source is IRQ_DMA7 (UART RX)

temp1=*pSIC_ISR;

temp1=IRQ_DMA7;

//p11-17 :DMA interrupt routines must explicitly write 1 to the corresponding DMA_IRQ_STATUS registers to clear the latched request of the pending interrupt.

*pDMA7_IRQ_STATUS = 1;

for (i=0;i<4;i++)

{

temp=RXbuf[i];

//TXbuf[i]=temp;

}

flag=1;

}

else

{

if(IRQ_DMA8 == (IRQ_DMA8 & *pSIC_ISR))

{

//Interrupt source is IRQ_DMA8 (UART TX)

//p11-17 :DMA interrupt routines must explicitly write 1 to the corresponding DMA_IRQ_STATUS registers to clear the latched request of the pending interrupt.

*pDMA8_IRQ_STATUS = 1;

if (flag==1)

{

flag=0;

TXbuf[0]=111;

TXbuf[1]=107;

TXbuf[2]=33;

TXbuf[3]=33;

}

}

}

}

void Init_gpio(void)

{

//p7-3: Port F & Port G Multiplexing Scheme. Multi-Function is controlled by the PORTF_MUX and PORTF_FER registers.

//p7-22: Function Enable Registers (PORTx_FER)

//For all bits, 0 - GPIO mode, 1 - Enable peripheral function

*pPORTF_FER |= PF11 | PF12 ; //ÅäÖÃPF11,PF12ÎaìØêa1|Äü½Å

//p7-21: Port Multiplexer Control Register (PORTx_MUX)

//For all bit fields: 0 = Peripheral function, 1 = Alternate peripheral function

*pPORTF_MUX &= ~(PF11 | PF12 );//ÅäÖÃPF11,PF12ÎaUART½ó¿ú¡￡

//p7-22: Function Enable Registers (PORTx_FER)

//For all bits, 0 - GPIO mode, 1 - Enable peripheral function

*pPORTG_FER &= (~(PG0 | PG1 | PG2 | PG3));

//p7-22: GPIO Direction Registers (PORTxIO_DIR)

//For all bits, 0 - Input, 1 - Output

*pPORTGIO_DIR |= (PG0 | PG1 | PG2 | PG3);

}