// 源码
short sFrame[858*5];
bool Set_PACK32 = true;
bool Set_Entire_Field = true;
int nCount = 0;
int nCount1 = 0;
int main( void )
{
nCount1 = 0;
Set_PLL(14,4); // 内核时钟:27MHz *14 = 378MHz 378MHz / 4 = 94.5MHz 内核时钟:25MHz *16 = 400MHz 系统时钟:400MHz / 4 = 100MHz
InitPPI0(Set_Entire_Field, Set_PACK32, PIXEL_PER_LINE, LINES_PER_FRAME);
InitInterrupts_coreA();
EnablePPI0();
while(1)
{
nCount++;
}
return 0;
}
oid InitInterrupts_coreA(void)
{
// configure interrupt
*pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00000000;
*pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x00000001; // map DMA0 PPI Interrupt -> IVG8
*pSIC_IAR2 = *pSIC_IAR2 & 0xffffffff | 0x00000000;
ssync();
register_handler(ik_ivg8, PPI0_RxIsr); // assign ISR to interrupt vector
ssync();
*pSIC_IMASK=0xffffffff; // 不屏蔽也没有中断
ssync();
}
EX_INTERRUPT_HANDLER(PPI0_RxIsr)
{
nCount1++;
}
void InitPPI0(bool entire_field, bool pack32,short pixel, short lines)
{
short transfer_length_bytes = ((pack32) ? 4 : 1);
// configure PPI0 - not enabled yet
*pPPI_CONTROL = (entire_field << 2) | FLD_SEL | (pack32 << 7)| (pack32 << 8);
*pPPI_FRAME = lines;
ssync();
// configure DMA for PPI0 - not enabled yet
*pDMA1_X_COUNT = pixel * sizeof(short) / transfer_length_bytes; // 2 bytes for each pixel, count divided by four if 32-bit DMA transfers are done
*pDMA1_Y_COUNT = 5;
*pDMA1_X_MODIFY = transfer_length_bytes;
*pDMA1_Y_MODIFY = transfer_length_bytes;
*pDMA1_START_ADDR = sFrame;
// 停止模式
*pDMA1_CONFIG = 0x1000 | 0x0000 | DI_EN | DMA2D | (pack32 << 3) | WNR;
ssync();
}
void DisablePPI0(void)
{
// disable transfers
*pPPI_CONTROL &= ~PORT_EN;
ssync();
*pDMA1_CONFIG &= ~DMAEN;
ssync();
}
void EnablePPI0(void)
{
// enable transfers
*pDMA1_CONFIG |= DMAEN;
ssync();
*pPPI_CONTROL |= PORT_EN;
ssync();
}
void Set_PLL(int pmsel,int pssel)
{
int new_PLL_CTL;
*pPLL_DIV = pssel;
asm("ssync;");
new_PLL_CTL = (pmsel & 0x3f) << 9;
*pSIC_IWR |= 0xffffffff;
if (new_PLL_CTL != *pPLL_CTL)
{
*pPLL_CTL = new_PLL_CTL;
asm("ssync;");
asm("idle;");
}
}
「该帖子被 red_wlh 在 2012-09-05 11:08:35 编辑过」