/* Set input or output */
SRU(LOW, DAI0_PBEN01_I); // Source D0
SRU(LOW, DAI0_PBEN02_I); // Source D1
SRU(LOW, DAI0_PBEN03_I); // Source MCLK
SRU(LOW, DAI0_PBEN05_I); // Source BCLK
SRU(LOW, DAI0_PBEN06_I); // Source LRCLK
SRU(LOW, DAI0_PBEN07_I); // Source D2
SRU(LOW, DAI0_PBEN08_I); // Source D3
SRU(LOW, DAI0_PBEN09_I); // Source D4
SRU2(HIGH, DAI1_PBEN01_I); // Destination D0 (KleerNet)
SRU2(HIGH, DAI1_PBEN02_I); // Destination D1 (KleerNet)
SRU2(HIGH, DAI1_PBEN03_I); // Destination MCLK
SRU2(HIGH, DAI1_PBEN05_I); // Destination BCLK
SRU2(HIGH, DAI1_PBEN06_I); // Destination LRCLK
SRU2(HIGH, DAI1_PBEN07_I); // Destination D2 (KleerNet)
SRU2(HIGH, DAI1_PBEN08_I); // Destination D0 (AMP)
SRU2(HIGH, DAI1_PBEN09_I); // Destination D1 (AMP)
SRU2(HIGH, DAI1_PBEN10_I); // Destination D2 (AMP)
/* FS/CLK/DAT to ASRC Input */
SRU(DAI0_PB06_O,SRC0_FS_IP_I);
SRU(DAI0_PB05_O,SRC0_CLK_IP_I);
SRU(DAI0_PB01_O,SRC0_DAT_IP_I);
/* PCG to ASRC Output */
SRU(PCG0_FSA_O,SRC0_FS_OP_I);
SRU(PCG0_CLKA_O,SRC0_CLK_OP_I);
/* External clock to PCG input*/
SRU(DAI0_CRS_PB03_O,PCG0_EXTCLKA_I);
/* PCG out to SPORT0B input*/
SRU(PCG0_FSA_O,SPT0_BFS_I);
SRU(PCG0_CLKA_O,SPT0_BCLK_I);
/* ASRC data to SPORT 0B*/
SRU(SRC0_DAT_OP_O,SPT0_BD0_I);
/* PCG clock to DAC clock*/
SRU2(PCG0_CRS_CLKA_O ,DAI1_PB05_I);
/* PCG FS to DAC FS*/
SRU2(PCG0_CRS_FSA_O ,DAI1_PB06_I);
/* PCG clk to DAC mclk */
SRU2(PCG0_CRS_CLKB_O,DAI1_PB03_I);
/* PCG clk/fs to SPORT4*/
SRU2(DAI1_PB05_O ,SPT4_ACLK_I);
SRU2(DAI1_PB06_O ,SPT4_AFS_I);
/*Sport data to DAC data*/
SRU2(SPT4_AD0_O,DAI1_PB08_I);
/*Sport data to DAC data*/
SRU2(SPT4_AD0_O,DAI1_PB09_I);
/*Sport data to DAC data*/
SRU2(SPT4_AD0_O,DAI1_PB10_I);
您的位置：
2021/11/8 17:44:22
