void speed_w_test(void)
{
long i,cont;
volatile unsigned int *DDRdata;
DDRdata=0;
for(i=0;i<0x8000000;i++)
{
if(i%2)
{
*DDRdata=0xaaaaaaaa;
DDRdata++;
}
else
{
*DDRdata=0x55555555;
DDRdata++;
}
}
}
void speed_r_test(void)
{
long i,cont,temp1;
volatile unsigned int *DDRdata;
DDRdata=0;
for(i=0;i<0x8000000;i++)
{
if(i%2)
{
temp1=*DDRdata;
DDRdata++;
if(temp1 !=0xaaaaaaaa)
printf("error! i is %x,temp1 is %x\n",i,temp1);
}
else
{
temp1=*DDRdata;
DDRdata++;
if(temp1 !=0x55555555)
printf("error! i is %x,temp1 is %x\n",i,temp1);
}
}
}
16位遍历代码：
void speed_w_test2(void)
{
long i,cont;
volatile unsigned short *DDRdata;
DDRdata=0;
for(i=0;i<0x8000000;i++)
{
if(i%2)
{
*DDRdata=0xaaaa;
DDRdata++;
}
else
{
*DDRdata=0x5555;
DDRdata++;
}
}
}
void speed_r_test2(void)
{
long i,cont,temp1;
volatile unsigned short *DDRdata;
DDRdata=0;
for(i=0;i<0x8000000;i++)
{
if(i%2)
{
temp1=*DDRdata;
DDRdata++;
if(temp1 !=0xaaaa)
printf("error! i is %x,temp1 is %x\n",i,temp1);
}
else
{
temp1=*DDRdata;
DDRdata++;
if(temp1 !=0x5555)
printf("error! i is %x,temp1 is %x\n",i,temp1);
}
}
}
初始化SDRAM：
void InitSDRAM(void)
{
if (*pEBIU_SDSTAT & SDRS)
{
*pEBIU_SDBCTL = 0x13131313; /*SDRAM Memory Bank Control Register*/
ssync();
*pEBIU_SDRRC = 0x000003a9; /*SDRAM Refresh Rate Control Register*/
ssync();
*pEBIU_SDGCTL = 0x0091998f; /*SDRAM Memory Global Control Register*/
ssync();
}
}
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0; // <--|Write access time = 7 cycles, read access time = 11 cycles, no ARDY
*pEBIU_AMBCTL1 = 0x7bb07bb0; // |Hold time = 2 cycles, setup time = 3 cycles, transition time = 4 cycles
*pEBIU_AMGCTL = 0x01FF; // |Enable all memory banks
}//end Init_EBIU
561xml文件更改部分：
<register-reset-definitions>
<register name="EBIU_SDRRC" reset-value="0x03a9" core="Common" />
<register name="EBIU_SDBCTL" reset-value="0x13131313" core="Common" />
<register name="EBIU_SDGCTL" reset-value="0x0091998f" core="Common" />
</register-reset-definitions>
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2018/5/11 16:12:27
