struct DmaDescListMode *pNext; /*!< Next list descriptor work unit in the chain */
void *pStartAddress; /*!< Start address of the data buffer to be processed */
uint32_t Config; /*!< DMA Configuration register - Specify Transfer word size (MSIZE/PSIZE) and Trigger configuration */
uint32_t XCount; /*!< Inner loop count start value in number of DMA data bus width (MSIZE) transfers */
int32_t XModify; /*!< Inner loop address increment in bytes */
uint32_t YCount; /*!< Outer loop count start value in number of rows */
int32_t YModify; /*!< Outer loop address increment in bytes */
bool bCallbackWhenDone; /*!< TRUE to notify application via callback on completion of this work unit */
DMA_DESC_LIST_MODE ScrList[3];
DMA_DESC_LIST_MODE DesList[3];
//section ("sdram0_bank3") unsigned char DestDataBuf[900000];
/***** Instances to handle List descriptor transfers ******/
/*============= C O D E =============*/
volatile int InProgress=1;
void DEST_MDMA_Handler0 (void);
void MemCopyListMode(unsigned char *SrcDataBufXC,unsigned char *DestDataBufXC)
{
adi_int_InstallHandler(INTR_MDMA0_DST, DEST_MDMA_Handler0, 0, true);
/* Prepares data buffers for Memory DMA copy */
//配置需要注意事项：1.把最后的一组描述符配置为stop模式。
//2.Config要配置成(ENUM_DMA_CFG_DSCLIST | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_EN)
for (char i = 0; i <2; i++)
{
ScrList[i].pStartAddress = SrcDataBufXC+i * 200;
ScrList[i].Config = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_READ| ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_DSCLIST;
//ENUM_DMA_CFG_DSCLIST | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_EN
ScrList[i].XCount = 200;
ScrList[i].XModify = 1;
ScrList[i].YCount = 1000;
ScrList[i].YModify = 1;
ScrList[i].bCallbackWhenDone = false;
//DMA Config - only specify memory transfer size
DesList[i].pStartAddress = DestDataBufXC+i * 200;
DesList[i].Config = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_WRITE| ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_DSCLIST;
DesList[i].XCount = 200;
DesList[i].XModify = 1;
DesList[i].YCount = 1000;
DesList[i].YModify = 1;//
DesList[i].bCallbackWhenDone = false;
ScrList[i].pNext = &ScrList[i+1];
DesList[i].pNext = &DesList[i+1];
}
ScrList[2].pNext = NULL;
DesList[2].pNext = NULL;
ScrList[2].pStartAddress = SrcDataBufXC+2*200;
ScrList[2].Config = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_READ| ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_DSCLIST;
//ENUM_DMA_CFG_DSCLIST | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_EN
ScrList[2].XCount = 200;
ScrList[2].XModify = 1;
ScrList[2].YCount = 1000;
ScrList[2].YModify = 1;
ScrList[2].bCallbackWhenDone = false;
//DMA Config - only specify memory transfer size
DesList[2].pStartAddress = DestDataBufXC+2 * 200;
DesList[2].Config = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_WRITE| ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_DSCLIST;
DesList[2].XCount = 200;
DesList[2].XModify = 1;
DesList[2].YCount = 1000;
DesList[2].YModify = 1;//
DesList[2].bCallbackWhenDone = false;
/* IF (End of list) */
ScrList[2].Config &= ~BITM_DMA_CFG_FLOW;//把最后一组描述符置为stop
DesList[2].Config &= ~BITM_DMA_CFG_FLOW;//
DesList[2].Config |= ENUM_DMA_CFG_YCNT_INT;//
DesList[2].bCallbackWhenDone = true;
ssync();
/* Prepares descriptors for Memory DMA copy */
/* configure source registers */
*pREG_DMA21_DSCPTR_NXT=ScrList;
*pREG_DMA21_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_READ | ENUM_DMA_CFG_DSCLIST ;//| ENUM_DMA_CFG_SYNC;
/* configure destination registers */
*pREG_DMA22_DSCPTR_NXT=DesList;
*pREG_DMA22_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_FETCH07 | ENUM_DMA_CFG_WRITE | ENUM_DMA_CFG_DSCLIST; //| ENUM_DMA_CFG_SYNC;
/* enable DMA */
//*pREG_DMA22_STAT |= ENUM_DMA_STAT_IRQDONE ;//clear the bit
ssync();
while(InProgress);
}
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2014/7/11 0:24:36
