void Init_BF538(void)
{
*pSIC_IWR |= 0x1;      // enable PLL wakeup
*pPLL_CTL = SET_MSEL(20);    // (25MHz Xtal x (MSEL=20))::CCLK=500MHz
idle();

*pPLL_DIV = SET_SSEL(4);    // (500MHz/(SSEL=4))::SCLK=125MHz  
ssync();
*pVR_CTL = 0x00DB;      // *pVR_CTL = 0x04DB;can bus setting
ssync();

*pEBIU_AMBCTL0 = 0xFFC2FFC2;
*pEBIU_AMBCTL1 = 0xFFC2FFC2;   //lowest speed for all bank
*pEBIU_AMGCTL = 0x00ff;    //all bank enalble                        
ssync();

*pEBIU_SDRRC = 0x074A; //0x03A3;  //SDRAM Refresh Rate Control Register
*pEBIU_SDBCTL = 0x0013; //0x0025;  //SDRAM Memory Bank Control Register
*pEBIU_SDGCTL = 0x8091998d;//0x998D0491;//SDRAM Memory Global Control Register
ssync();

    *pFIO_FLAG_C =PF1;     //先按4M Flash memory
    *pFIO_FLAG_C = PF5;
                                  
}

void Init_SPORT1(void)
{
    *pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xfff2ffff;
*pSIC_IAR2 = 0xffffffff;

register_handler(ik_ivg9, SPORT1TX_ISR);

*pSIC_IMASK = 0x00001000;

  *pSPORT1_TCR1 |=IRFS|RFSR|IRCLK;      
  *pSPORT1_TCR2 = 31;      
  *pSPORT1_TCLKDIV = 7;      
  *pSPORT1_TFSDIV = 9;

}
EX_INTERRUPT_HANDLER(SPORT1TX_ISR)
{
if( *pSPORT1_STAT & TXHRE )
{
  *pSPORT1_TX =0x7865;
}
}
main()
{
Init_BF538();
Init_SPORT1();
*pSPORT1_TCR1 = (*pSPORT1_TCR1|TSPEN);
while(1);
}