#include <cdefBF518.h>
#include <ccblkfn.h>
#include "audio_regdef.h"
#define AIC23B_ADDRESS 0x34
#define PRESCALE_VALUE 8
#define RESET_TWI 0 /* RESET_TWI value for controller */
#define CLKDIV_HI 66 /* SCL high period */
#define CLKDIV_LO 67 /* SCL low period */
int TWISuccess;
unsigned char AudioConfig[] = {
PWDC, 0x00FF,
LLVC, 0x1d,
RLVC, 0x1d,
LHVC, 0x78,
RHVC, 0x78,
AAPC, 0xf5,
DAPC, 0,
PWDC, 1,
DAIF, MS|FOR|LRP,
SARC, 0,
DIAC, ACT|RES
};
unsigned char AudioColse[]={
RSRE, 0
};
void delay(int tem)
{
int j,i;
for(i=tem;i>0;i--)
{
for(j=1000;j>0;j--)
{
j=j;
}
}
}
/*******************************************************************
* Function: Reset_TWI
* Description: reset the TWI interface
*******************************************************************/
void Reset_TWI(void)
{
/* reset TWI controller */
*pTWI_CONTROL = RESET_TWI; //#define RESET_TWI 0 /* RESET_TWI value for controller */
ssync();
/* clear errors before enabling TWI */
*pTWI_MASTER_STAT = BUFWRERR | BUFRDERR | LOSTARB | ANAK | DNAK;
ssync();
/* clear interrupts before enabling TWI */
*pTWI_INT_STAT = SINIT | SCOMP | SERR | SOVF | MCOMP | MERR | XMTSERV | RCVSERV;
ssync();
/* flush rx and tx fifos */
*pTWI_FIFO_CTL = XMTFLUSH | RCVFLUSH;
ssync();
/* set this to 1 so that we go into the write sequence the very first time */
TWISuccess = 1;
}
/*******************************************************************
* Function: ClrSclSda
* Description: restores control of the TWI interface
*******************************************************************/
bool ClrSclSda(void)
{
int cnt = 0;
do {
*pTWI_MASTER_CTL = SCLOVR;
delay(6);
*pTWI_MASTER_CTL = 0;
delay(6);
} while ((*pTWI_MASTER_STAT & SDASEN) && (cnt++ < 8));
*pTWI_MASTER_CTL = SDAOVR | SCLOVR;
delay(6);
*pTWI_MASTER_CTL = SDAOVR;
delay(6);
*pTWI_MASTER_CTL = 0;
return ((*pTWI_MASTER_STAT & SDASEN) || (cnt == 8)) ? false : true;
}
/*******************************************************************
* Function: TWI_MasterMode_Write
* Description: do a master mode write
*******************************************************************/
void TWI_MasterMode_Write(unsigned char DeviceAddr, unsigned char *TWI_Data_Pointer, unsigned short Count, unsigned char TWI_Length)
{
int i, j, timeout;
if (*pTWI_MASTER_STAT & SDASEN)
{
if(!ClrSclSda())
return;
}
/* make sure no previous errors occured */
if (TWISuccess == 1)
{
*pTWI_FIFO_CTL = 0; /* clear the bit manually */
*pTWI_CONTROL = TWI_ENA | PRESCALE_VALUE | SCCB; /* PRESCALE = fsclk/10MHz */
*pTWI_CLKDIV = ((CLKDIV_HI) << 8) | (CLKDIV_LO); /* CLKDIV = (1/SCL)/(1/10MHz) */
*pTWI_MASTER_ADDR = DeviceAddr; /* target address (7-bits plus the read/write bit) */
for (i = 0; i < Count; i++)
{
/* # of configurations to send */
*pTWI_XMT_DATA8 = *TWI_Data_Pointer++; /* pointer to data */
ssync();
*pTWI_MASTER_CTL = (TWI_Length<<6) | MEN /*| FAST*/; /* start transmission */
timeout = 0x1000;
for (j = 0; j < (TWI_Length-1); j++)
{
/* # of transfers before stop condition */
while ((*pTWI_FIFO_STAT == XMTSTAT) && --timeout) /* wait to load the next sample into the TX FIFO */ // TAR37913
{
ssync();
}
if(!timeout)
return;
*pTWI_XMT_DATA8 = *TWI_Data_Pointer++; /* load the next sample into the TX FIFO */
ssync();
}
timeout = 0x1000;
while (!(*pTWI_INT_STAT & MCOMP) && --timeout) /* wait until transmission complete and MCOMP is set */
{
ssync();
}
if(!timeout)
return;
/* check if an error occured */
if ((*pTWI_INT_STAT & MERR) == MERR)
{
*pTWI_INT_STAT |= MERR;
TWISuccess = 0;
}
*pTWI_INT_STAT = XMTSERV | MCOMP; /* service TWI for next transmission */
}
}
asm("nop;");
asm("nop;");
asm("nop;");
}
/*******************************************************************
* Function: TWI_MasterMode_Read
* Description: do a master mode read
*******************************************************************/
void TWI_MasterMode_Read(unsigned short DeviceAddr, unsigned char *TWI_Data_Pointer, unsigned short Count)
{
int i, j;
*pTWI_FIFO_CTL = 0; /* clear the bit manually */
*pTWI_CONTROL = TWI_ENA | PRESCALE_VALUE; /* PRESCALE = fsclk/10MHz */
*pTWI_CLKDIV = ((CLKDIV_HI) << 8) | (CLKDIV_LO); /* CLKDIV = (1/SCL)/(1/10MHz) */
*pTWI_MASTER_ADDR = DeviceAddr; /* target address (7-bits plus the read/write bit) */
*pTWI_MASTER_CTL = (Count<<6) | MEN | MDIR /*| FAST*/; /* start transmission */
/* for each item */
for (i = 0; i < Count; i++)
{
while (*pTWI_FIFO_STAT == RCV_EMPTY) /* wait for data to be in FIFO */
ssync();
*TWI_Data_Pointer++ = *pTWI_RCV_DATA8; /* read the data */
ssync();
}
while ((*pTWI_INT_STAT & MCOMP) == 0) /* wait until transmission complete and MCOMP is set */
ssync();
*pTWI_INT_STAT = RCVSERV | MCOMP; /* service TWI for next transmission */
asm("nop;");
asm("nop;");
asm("nop;");
}
void iic_init(void)
{
int j;
int TWI_Error = 0;
TWISuccess = 0;
while (TWISuccess == 0 && TWI_Error < 100)
{
TWISuccess = 1;
Reset_TWI(); /* reset the TWI interface */
TWI_MasterMode_Write( AIC23B_ADDRESS>>1, AudioConfig, 11, 2);
if(TWISuccess)
for (j=0; j<0x1ffffff; j++) asm("nop;");
/*** lastly activate the digital engine *******************/
if(!TWISuccess)
TWI_Error++;
}
}
void audio_close(void)
{
int j;
int TWI_Error = 0;
TWISuccess = 0;
while (TWISuccess == 0 && TWI_Error < 100)
{
TWISuccess = 1;
Reset_TWI(); /* reset the TWI interface */
TWI_MasterMode_Write( AIC23B_ADDRESS>>1, AudioColse, 1, 2);
if(TWISuccess)
for (j=0; j<0x1ffffff; j++) asm("nop;");
/*** lastly activate the digital engine *******************/
if(!TWISuccess)
TWI_Error++;
}
}
这个程序是你们提供的bf51x_audio_mic中的程序，TWI的配置是按这个来吧，还要配置其他的寄存器吗，这个实时时钟是不是要配置成SLAVE模式？
您的位置：
2017/9/14 16:38:38
